1. Field of the Invention
This invention relates to semiconductor memory and, more particularly, to a content addressable memory (CAM) cell design that employs straight polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) word lines and no more than two metal layers, is relatively small and symmetrical in layout, and consumes minimal power during read and write operations.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Semiconductor memory is generally configured upon a substrate as an array of storage cells. Random access memory (RAM) is a special type of semiconductor memory than can examine stored data within one storage cell independent of data within another storage cell. Reading data from or writing data to a RAM involves first addressing the particular storage cell of interest. Accordingly, a user will supply an address to the array for selecting one or more storage cells, and then read to or write from the addressed storage cells.
The efficiency by which a user can access information within a RAM is somewhat dependent on the address bus size. For example, an 8-bit bus can address 256 storage cells in random fashion. Depending on the size of the RAM, multiple accesses may be needed to address the storage cell of interest.
In addition to its depth, RAM memory accesses limited by the number of address lines employed, and the size of each RAM cell is dependent on whether the memory device is a dynamic RAM or static RAM. A static RAM or SRAM uses six transistors per cell. Four transistors are cross-coupled to form a bi-stable latch, and two transistors are used to alter or read out the state of bits stored in the bi-stable latch. An SRAM cell is larger in size than the typical one-transistor dynamic RAM (or DRAM). Unfortunately, however, the stored bit in the DRAM cell must be periodically restored or refreshed.
Data is often organized within the SRAM or DRAM storage cells in an organized, or structured fashion. For example, bursts of data are stored in adjacent word cells so they can be quickly accessed by the address bus. However, multiple accesses may be needed to determine the location of data within the RAM device.
Contrary to DRAMs and SRAMs content addressable memories (CAMs) do not store data in any structured fashion. The locations at which data is stored within CAM can be merely random, where the data can be written directly into the first empty location within the CAM. Once data is stored in CAM, it can be found by comparing every bit in the CAM memory cells with data placed in a comparand register. If a match exists for every bit stored in a particular location within the CAM corresponding to every bit in the comparand, a match line is asserted. A priority encoder can then sort out which matching location among multiple match lines has the top priority.
CAM devices are unique in that a user generally supplies the data and receives back an address for that data. Because the CAM does not require address lines to find data, the depth of the CAM can be extended as far as desiredxe2x80x94well beyond the depth of a RAM.
A CAM device is useful in any application requiring fast searches of a database, lists, or pattern, and supplies heightened performance advantages over other memory search algorithms, such as binary or tree-based searches or look-aside tag buffers. Currently, CAMs are particularly well suited for handling packet protocols, such as TCP/ IP protocols employed in packet processors that are used to route information across the an intranet or internet. These useful functions, however, are limited based on the sheer size of a CAM cell relative to SRAM or DRAM cells. Typically, each CAM cell must also have exclusive NOR circuitry. The exclusive NOR circuit is used to perform the compare data stored in the comparand register with data in the storage cell. Depending on whether the CAM cell is a binary or ternary CAM cell, additional transistors may be needed to store masked bits or xe2x80x9cdon""t carexe2x80x9d bits. For example, a CAM cell based on the SRAM platform may require more than 16 transistors per cell compared to the six transistor arrangement of a non-CAM, SRAM cell. In addition to its large size, many CAM cells multiplex the bit lines and compare lines. Whenever the CAM cell tries to read or write a bit, activity upon the bit line may cause periodic power consumption within the exclusive NOR compare circuitry. For example, the bit line and stored data within the CAM cell may temporarily transition, such that when placed on the gate conductors of the exclusive NOR series-connected transistors, transient connection between power and ground may occur. This condition could persist for a relatively long period of time during the read or write cycles.
It would be advantageous to implement an improved CAM cell design that is relatively small in size, employs minimal transistors, is symmetric in layout, and consumes minimal power during read and write operations. The desired CAM cell should advantageously use a minimal number of processing layers, and preferably use a minimal number of conductive layers. By reducing the number of layers within the manufacturing process, substantial cost savings and manufacturing throughput can be had.
The problems outlined above are in large part solved by an improved content addressable memory device containing a plurality of content addressable memory cells. Each cell preferably includes a compare circuit and a selection circuit. The selection circuit may include a multiplexer, where the multiplexer is used to selectably couple power or ground to the compare circuit depending on whether the memory cell is servicing a read/write operation or a compare operation. During times when a read/write operation occurs, the multiplexer will forward power to the compare circuit to ensure that no matter what voltage level is placed on the bit line, the logic value on bit line forwarded to one of the exclusive NOR transistors of the compare circuit will not cause a transient low resistive state between the match line and the node on which power is coupled. The match line is normally placed in a pull-up condition. If the common node on the other side of the series-connected transistors of the exclusive NOR arrangement is also at power, then there can be no temporary low resistance path between power and ground. Accordingly, during a read or write operation, having both ends of the series-connected transistors connected to power will substantially eliminate power consumption within the compare circuit during the read and write operations.
The selection circuit can also be used to selectively place ground onto the compare circuit during a compare operation. In this manner, the series-connected transistors of the exclusive NOR configuration have power and ground connected at the opposing ends of the series-connected transistors. The match line is pulled to power, while the common node of the compare circuit is placed at ground, a combination of both will render the compare circuit active only during the compare operation.
The selection circuit can therefore sense when the CAM cell is undergoing a read/write operation or a compare operation. Depending on which operation is being undertaken, the selection circuit will enable either a power supply or a ground supply to be placed on the common node, or source node, of the series-connected pair of transistors.
According to another embodiment, the CAM device includes a plurality of CAM cells arranged in an array across a semiconductor substrate. Each row of memory cells can be formed by rotating adjacent horizontally extending cells within the row about a y-axis extending vertically through the center of the memory cells. A column of memory cells can be formed by rotating adjacent vertically extending cells within the column about an x-axis extending horizontally through the memory cells. In this fashion, the neighboring memory cell to the immediate right of the previous memory cell can be formed by duplicating by rotating the previous cell about the y-axis, and then placing the rotated memory cell so that it abuts the rightmost boundary of the previous memory cell. This process is repeated across the substrate to form a row of memory cells. The same can be said for forming a column of memory cells. A previous memory cell can be extended upward to form a column by taking the previous memory cell and rotating it about the x-axis to form a duplicative memory cell that is placed directly above the previous memory cell and which abuts the topmost boundary of the previous memory cell. This process is repeated to form the entire column of memory cells.
Preferably, the size of each memory cell within the array of memory cells is less than approximately 4 microns by 1.5 microns for gate lengths (or critical dimensions) of approximately 0.15 micron. As critical dimensions increase or decrease, the cell size will increase or decrease proportionally. For example, if the critical dimension is 0.1 micron instead of 0.15 micron, then not only would critical dimension decrease by approximately 33%, but also the corresponding cell would decrease by approximately 33% in each direction. The opposite would occur if the critical dimension increases.
The array of memory cells are preferably interconnected using local and global metal, or metal alloy conductors. The conductors can be made from any metallic substance, such as copper, aluminum, etc. Preferably metal interconnection is effectuated on no more than two metal layers. Each memory cell comprises no more than eight metal conductors on a first metal layer, and comprises two bit lines or compare lines on a second metal layer. The eight metal lines on the first metal layer extend across the entire cell, and the two bit/compare lines also extend across the entire cell. The eight metal lines are parallel to each other and extend perpendicular to the bit/compare lines on the second metal layer. Also arranged upon the second metal layer are local metal interconnects. Unlike the bit/compare lines and the eight lines on the first metal layer, the local interconnects do not extend xe2x80x9cgloballyxe2x80x9d across the entire cell. The local interconnects are used to route power and ground from conductors on the first metal layer to corresponding vias arranged over active areas configured to receive the power and ground supplies. Thus, the local interconnect within the second metal layer affords use of only a single, globally extending power conductor and a single, globally extending ground conductor per cell. In addition to power and ground conductors, the first metal layer also includes three word lines that are periodically coupled to underlying polycrystalline silicon, or xe2x80x9cpolysiliconxe2x80x9d, conductors which form the gates of the pass-through transistors within a row of storage cells. The polysilicon conductor, when programmed to receive power, activate transistors within each storage cell and mask storage cell to access the corresponding stored bits and masked stored bits during a read/write operation. The polysilicon conductor is substantially straight and lies directly beneath the substantially straight data word line, global word line, and mask word line conductors on the first metal layer.
One of the eight conductors within the metal one layer can selectively receive power or ground. In particular, this conductor is coupled to the output of the select circuit, or multiplexer, to receive power or ground depending on whether the enable signal forwarded to the multiplexer enables either power or ground.
According to yet another embodiment, a method is provided for minimizing power consumption within a CAM cell. The method includes applying power to a compare circuit within the memory cell during a first time in which the memory cell is undergoing a read or write operation. Thereafter, ground can be applied to the compare circuit within the memory cell during a second time in which the memory cell is undergoing a compare operation. Of course, if the compare circuitry uses p-channel transistors instead of n-channel transistors, then the multiplexer would apply power, instead of ground, during a compare operation, and would apply ground, instead of power, during a read/write operation. In the example provided, n-channel transistors are used in the compare circuitry.